Stare and forward mechanisms, particularly in X25 and frame relay applications, are widely known in the telecommunication field. They allow the transfer of packets of data through the different nodes of the network. The integrity of data transmitted throughout the network is a key problem to telecommunication developers. Two main sources of errors actually may affect the communication.
First, erroneous data might be introduced in the frame as it is transmitted from one node to another. Such errors are effectively detected by using well known Frame Checking Sequences (FCS) or CRC checksums involved in the High Data Link Control (HDLC) procedures. In such mechanisms, the transmitting station sends a packet and appends to it an appropriate computed CRC checksum. At the other end of the line, the receiving node stores the transmitted checksum, calculates its own CRC checksum, and compares the two checksumsto detect the occurrence of a possible error during the transmission of the packet through the line.
However, although errors can alter the data during its transmission through the line, frames can unfortunately be affected during their processing inside a telecommunication node, for example, during storage in the RAM storage of the machine. Indeed, after the above comparison of the transmitted checksum and the computed checksum, the received frame including a header field and a data field is stored into the storage of the machine before any further processing. Then, a processor also included in the machine separates the header field and processes it according to the address to which the packet is to be delivered and then generates another header. Then, a further new CRC checksum is computed which corresponds to both the new header and the data field and a new frame comprising the new header, the data field and the new checksum is transmitted to the next telecommunication node. During the above processing of the frame, errors might unfortunately be introduced within the memory since RAM storages are sensitive to electrostatic discharges, alpha particles, glitches, and other noise sources. Errors might also be introduced during the storage of data in memory at the BUS level, i.e. DMA error. It appears that those errors are introduced within the frame after the checking of the received CRC checksum which was computed by the preceeding telecommunication node, and before the computation of the next CRC checksum which will be appended to the packet when it is transmitted to the further telecommunication node. Consequently, errors which have occurred during the processing of the frame can not be detected by the traditional store and forward mechanisms.
Since store and forward mechanisms process a large number of packets, it is highly desirable to assure the integrity of data during its storage within the PAM of the machine without requiring further processing resources from the processor which are already affected to provided the required communication rate, and also without requiring supplementary data storage. Further, as it appears from the document Data Communication, Sep. 21, 1991, page 70, "one of the most significant sources of TCP/IP overhead is the delay associated with calculating the checksums used to verify the integrity of data. Before the transmitting station can send a packet, it must calculate the packet's checksum and append that checksum to the packet's header". It is therefore highly desirable to provide the data integrity during the transfer in RAM without requiring further processing resources which would first overload the processor and secondly involves a supplementary delay, thus requiring a larger storage capacity.